1. Field of the Invention
The present invention relates to pixel display circuits and, more particularly, to a circuit for providing integrated data and gate multiplexing without impact to acceptable standards for displays.
2. Description of the Related Art
Due to poor charging ability in amorphous silicon thin film transistors (a-Si TFTs) resulting from inherently low TFT transconductance, all commercially available a-Si TFT liquid crystal displays (LCD) include an array of pixel elements connected with row and column metal lines. The row and column drivers require higher transconductance devices. The row and column drivers typically include crystalline silicon technology and are separately fabricated and attached to the a-Si TFT LCDs. Over the years, there have been attempts at integrating some level of multiplexing between the attached crystalline silicon drivers and the pixel array. See for example, U.S. Pat. No. 5,175,446 to R. Stewart. In this way, the number of crystalline drivers needed could be reduced. These prior art designs follow a circuit approach that is commonly used in crystalline silicon circuit designs. Even simple 2:1 level multiplexing schemes at the edge of a pixel array have not been implemented for a-Si TFT LCD circuits. Although not realized for direct view a-Si TFT LCDs, multiplexer circuits have been implemented with some success in smaller displays for example, in light valves and in poly-silicon technology. Poly-silicon TFTs make it possible to realize a higher transconductance TFT. However, implementing poly-silicon technology on larger and/or high resolution TFT LCDs leads to an unacceptably higher RC load and/or higher bandwidth rates of the rows and columns.
Therefore, a need exists for a circuit for providing integrated data and gate multiplexing for active matrix LCDs without impacting acceptable display limits. A further need exists for a reduction in data drivers and gate drivers to reduce costs of these displays.
An active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array. At least two transistors associated with each pixel are included. The transistors are serially connected to each other and disposed within the array for switching the pixels on and off according to data and gate signals. A data line is coupled to a first end of the serially connected transistors for each pixel. A second end of the serially connected transistors is coupled to a storage device. The serially connected transistors provide multiplexing capability for at least one of data signal multiplexing and gate signal multiplexing.
Another active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array including rows and columns. At least two transistors associated with each pixel, the transistors being serially connected and positioned within the array for switching the pixels on and off. A plurality of data lines run substantially parallel to the columns. A plurality of scan lines run substantially parallel to the rows. The data lines and scan lines being coupled to the transistors of the pixels such that the data lines provide data multiplexing for each pixel and the scan lines provide gate multiplexing for each pixel.
In alternate embodiments of the displays in accordance with the invention, one of the at least two transistors may be shared between adjacent pixels to further reduce gate or data drivers. The pixels may modulate light in a transmissive mode and/or a reflective mode. The array preferably includes rows and columns and the control lines may select the pixels in different rows simultaneously. The simultaneously selected pixels may share a data line. Control lines may include data lines and the simultaneously selected pixels may each use a different data line. The control lines may includes scan lines and/or capacitance storage lines. The control lines may be coupled to the transistors by a low impedance contact path which may include a metal, polycrystalline silicon, a capacitor or a combination thereof. The display may include a liquid crystal display, and the transistors preferably include thin film transistors.
The data multiplexing may include L:1 multiplexing where L is an integer greater than one. The gate multiplexing may include m:1 multiplexing where m is an integer greater than one. The data lines may select pixels in different rows simultaneously, or the pixels may share a data line. The display may further include logic circuitry for controlling the multiplexing in accordance with control signals. The transistors are preferably disposed on a substrate and the pixels are formed over the transistors
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.